An integrated circuit (IC) contains various semiconductor devices and a plurality of conducting metal paths that provide electrical power to the semiconductor devices and allow these semiconductor devices to share and exchange information. Within an integrated circuit, metal layers are stacked on top of one another using intermetal or interlayer dielectric layers that insulate the metal layers from each other. Normally, each metal layer must form an electrical contact to at least one additional metal layer. Such electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the metal layers, and filling the resulting via with a metal to create an interconnect structure. Metal layers typically occupy etched pathways in the interlayer dielectric. A “via” normally refers to any micro-feature such as a hole, line or other similar feature formed within a dielectric layer that provides an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer. Similarly, micro-features containing metal layers connecting two or more vias are normally referred to as trenches.
A long-recognized objective in the constant advancement of integrated circuit (IC) technology is the scaling down of IC dimensions. Such scale down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of ICs. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. These advances are driving forces to constantly scale down IC dimensions. An increase in device performance is normally accompanied by a decrease in device area or an increase in device density. An increase in device density requires a decrease in via dimensions used to form interconnects, including a larger aspect ratio (i.e., depth to width ratio). As the minimum feature dimensions on patterned substrates (wafers) steadily decreases, several consequences of this downward scaling are becoming apparent. As the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, the small features are difficult to fill with bulk metal, leading to formation of voids in the bulk metal filling and electromigration (EM) failure, which may lead to open and extruded metal lines.
The introduction of copper metal into multilayer metallization schemes for manufacturing integrated circuits is enabled by the damascene copper metal plating process where bulk copper metal is used to fill vias and/or trenches, and a chemical mechanical polishing (CMP) process is performed to planarize the bulk copper metal. The copper metal plating process is now extensively used by manufacturers of advanced microprocessors and application-specific circuits. However, copper metal cannot be put in direct contact with dielectric materials since copper metal has poor adhesion to the dielectric materials and copper metal is known to easily diffuse into common integrated circuit materials such as silicon and dielectric materials where copper is a mid-bandgap impurity. Furthermore, oxygen can diffuse from an oxygen-containing dielectric material into copper metal, thereby decreasing the electrical conductivity of the copper metal. Therefore, a diffusion barrier material is formed on dielectric materials and other materials in the integrated circuits to surround the copper metal and prevent diffusion of the copper metal into the integrated circuit materials. A tantalum nitride/tantalum (TaN/Ta) bilayer is commonly used as a diffusion barrier/adhesion layer for copper metallization since the tantalum nitride barrier film adheres well to oxides and provides a good barrier to copper diffusion and the tantalum adhesion layer provides good bonding to both tantalum nitride on which it is formed and to the copper metal formed over it. However, a tantalum adhesion layer is easily oxidized which reduces its copper wetting properties.
Copper metal plating on interconnect structures usually requires a nucleation or seed layer (e.g., a copper metal seed layer) that is deposited over a substrate topography prior to copper metal plating. However, it is well known that copper metal agglomeration occurs when a copper metal seed layer is deposited on tantalum and many other materials at room temperature. The copper metal agglomeration results in a discontinuous copper metal seed layer. The copper metal agglomeration is detrimental to the subsequent copper metal plating process and frequently results in formation of voids in the plated bulk copper metal. In order to reduce the copper metal agglomeration on a tantalum adhesion layer, the copper metal seed layer is often deposited at a low substrate temperature, for example −25° C., −30° C., or even lower substrate temperatures, using a low-temperature electrostatic chuck (ESC) to support and maintain the substrate (wafer) at the low substrate temperature. However, the low substrate temperatures result in rough or irregular copper metal layers and do not eliminate the copper metal agglomeration on the tantalum adhesion layer and the formation of voids in the plated bulk copper metal.
Therefore, processing methods are needed for forming smooth non-agglomerated copper metal seed layers that allow void-free copper metal filling of small recessed features with high aspect ratios.